GLOBALFOUNDRIES SINGAPORE PTE. LTD. (Singapore, SG)

A method of forming devices is described. A substrate that has high gain (HG) device region to accommodate the HG transistor is disclosed. The device area of HG is used to form an HG gate. Sidewall spacers are included on the sides of the HG gate. The HG gate is situated in an area with significant levels of doping. The inner edges of these regions that are heavily doped are aligned to the outside edges of the sidewall spacers that form the HG gate. The regions that are heavily doped are HG source/drain (S/D) regions within the gate. The HG S/D regions do not contain halo or lightly doped drain regions.

Complementary Metal Oxide Semiconductor (CMOS) transistors are widely used. For example, CMOS transistors have been utilized in analog applications. Analog applications utilize the CMOS transistors which have high gains. It has been discovered that CMOStechnology is becoming more effective as it progresses to the nano-regime.

The present invention focuses on creating high-gain transistors within the nanotechnology range.

Embodiments generally relate to semiconductor devices, also known as integrated circuits (ICs). In one example, a method for making a device is explained. It is possible to provide an underlying substrate that has an area of high gain (HG) for a transistor that is an HG. A HG gate isformed on the substrate within the device region of HG. Spacers for sidewalls are incorporated into the sides of the HG gate. The heavily doped regions are located near the HG gate. Inner edges of the highly doped areas are aligned with the outer edges of the sidewall spaces of the HG gate. These regions are HG source/drain regions (S/D) of the gate HG. The HG S/D regions do not include lightly doped drain (LDD) regions, or halo regions.

A method of creating devices according to a different embodiment is also presented. This technique requires a substrate at least one device region for first transistors and one for second transistors. A first gate is formedon the first device region and the second gate is formed in the second device region. The gates include sidewall spacers on their sidewalls. They are situated in areas with significant levels of doping. The edges of these heavily doped areas are aligned with outer edges of sidewall spacers located at the gates. The heavily doped regions function as source/drain (S/D) regions in the gates. The S/D regions in the second transistor don’t include light doped drain (LDD) regions or Halo regions.

In yet another way the device is described. A substrate that has a high gain region (HG) to accommodate a transistor that is a HG is present in the device. A HG gate is disposed on the substrate within the HG device area. Sidewall spacers are included in the HG gate’s sidewalls. Heavily doped regions are disposed adjacent to the HG gate. The HG gate’s sidewall spacers are placed at the outer edges of the heavily doped regions. The regions that are heavily doped serve as HG source/drain (S/D)regions of the gate. The S/D regions in the HG gate don’t include lightly doped drain (LDD) regions or Halo regions.

These, as well as other advantages and advantages of the embodiments described herein are apparent with reference to the following description and the accompanying drawings. It is important to understand that the attributes that are described in various embodiments are not necessarily distinct. They are able to be combined and altered.

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