Semiconductor Energy Laboratory Co., Ltd. (Atsugi-shi, Kanagawa-ken, JP)
What is a Patent for Carbon nanotubes that are highly conductive that has bundle moieties, with low bulk density and its manufacturing method
This is a silicon structure which has a complex 3D shape. A simple and straightforward method of making the silicon structure is offered with the help of a phenomenon in which an ordered pattern is formed in a natural way to form an amorphous nano-structure. Plasma treatment under hydrogen is applied to an amorphous silicon layer , and the following processes are performed at the same time using a reaction procedure for growing microcrystalline silicon on the top layer of silicon and a reaction process for etching the silicon layer, which is exposed, so that the nano-structure, which includes an upper structure in microcrystalline form and one in an amorphous form on top of the silicon layer, is created. As a result it is possible to create a silicon structure having a three-dimensionally complex shape can be made.
1. Field of the Invention
The present invention is related to the silicon structure, a technique to manufacture the structure of silicon, as well as a method for manufacturing capacitors that include the structure of silicon.
2. Description of Related Art
In recent years, accuracy of microfabrication technique has been improving steadily, a nano-meter scale structure (a nano-structure) and nano-technology for manufacturing the nano-structure have attracted attention across a range of fields of electronics. As a method for manufacturing the nano-structure, a technique in which a pattern is directly created using the use of light or electron beams is typically used.
In contrast, there’s a method using the idea that an ordered pattern forms in a natural way to create the nano-structure, without the use of an artificial method, such as a lithography technique. Because a nano-structure is formed using this method the pattern doesn’t have to be created directly, so that nano-structures can be easily created over a wide area.
As an example of a nano-structure, there is hemispherical-grain-silicon (HSG-Si) (for example, Patent Document 1). The HSG-Si is hemispherical polysilicon grain. In Patent Document 1, the HSG-Si is fabricated on an electrode’s surface to increase the surface area of the electrode, and consequently storage capacity is enhanced.
[Patent Document 1] Japanese Published Patent Application No. H5-315543
A technique for forming the three-dimensional nanostructure with a shape that isn’t as complex as the hemispherical polysilicon described in Patent Document 1 has been previously disclosed. There are several methods that could create an atom-sized structure that has a more complicated three-dimensional shape, such as the shape that has constriction and swelling, as opposed to the one described above.
In particular, in the situation where a surface area of the electrode surface of a capacitor is increased by creating a projection and depression of the nano-structure as disclosed in Patent Document 1, the nano-structure is formed to have athree-dimensionally complex shape with constriction and swelling, and the surface area can be further increased.
A silicon layer that contains a complex three-dimensionally-constructed nano-structure is one embodiment of the invention. Another object of one embodimentof the present invention is to provide a process to fabricate the silicon structure quickly and easily, utilizing an occurrence in which an ordered pattern is formed in a natural way to create a nano-structure.
Amorphous silicon is subjected to treatment by plasma under hydrogen atmosphere. The following procedures can be performed simultaneously in a reaction process to create microcrystalline silica the silicon surface , and an action process to etch the exposed silicon layer. This results in the nanostructure, which has an upper structure in microcrystalline form and a lower structure in an unamorphous state. The following structures are able to be used, particularly.
One embodiment of the invention includes an amorphous layer of silicon and a plurality nano-structures that are created on top of this layer. The nano-structure comprises a lower structure containing the amorphous silicon, and an upper one containing microcrystalline silicon and overlapping with the lower structure. The silicon structure, the size of the lower structure in the horizontal direction, which is the direction substantially parallel to the top of the silicon layer that is amorphous is smaller than or equal to the width of the upper structure in the horizontal direction, in the cross section of the lower structure and the upper structure.
It is recommended to ensure that the width in the horizontal direction be gradually decreased from a peripheral part of the structure having the maximum width in the horizontal direction , to the lower structure of the cross-section of the lower and upper structure. Additionally the silicon atom in the lower structure as well as the silicon atom that is contained in the amorphous silicon layer preferably form a covalent bond. Additionally, the top-surface of the upper structure should be curved. Additionally, an impurity component that has one type of conductivity can be added to the silicon layer and the nano-structure.
Another embodiment of the present invention is a cap that includes the silicon structure as well as an insulating layer that is placed over the silicon structure as well as an electrode layer on top of the insulating layer. Additionally, a different embodiment of the presentinvention is a capacitor comprising the silicon structure, a second electrode layer that is placed over the silicon structure and an insulating layer on top of the first electrode layer and an additional electrode layer on top of the layer of insulation.
A different embodiment of the invention is a method of manufacturing a silicon structure by applying plasma treatment under hydrogen atmosphere on an amorphous silicon surface to grow microcrystalline silicon on a surface of the amorphoussilicon layers, such that a number of upper structures is formed while at the same time, to etch the silicon layer, which is exposed in a manner that a number of lower structures beneath the upper structures are formed and a variety of nano-structures, each of which is made up of the upper structure and the lower structure over the amorphous silicon layer is formed.
For the plasma treatment it is preferred that the pressure be 5 kPa or higher and that the power be 1000 W or more. It is also preferable for the treatment to be performed at 20 kPa or less power, with the maximum power of 2000W. When treating with plasma, it is preferred that the temperature of the substrate not exceed 200 degrees. C. to 300.degree. C. It is recommended to have the deposition of Amorphous Silicon and the plasma treatment be successively performed without exposure to air.
An amorphous layer of silicon is subjected to plasma treatment under the hydrogen atmosphere. The following processes are also carried out simultaneously: A reaction process for growing microcrystalline silica on the silicon layer and an action process to etch the silicon layer. This produces an amorphous nanostructure that has an upper structure in microcrystalline structure and lower in an unamorphous state. In the end, it is possible to provide a silicon structure with an intricate three-dimensional structure.
Additionally, the above-mentioned method can be utilized to create a silicon structure in a short time and with ease with a process that allows for the formation of an ordered pattern in a single step to form the nano-structure.
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